1. Field of the Invention
The present invention relates to a three-dimensionally stacked nonvolatile semiconductor memory.
2. Description of the Related Art
A bit cost scalable (BiCS) technique is known as a technique for achieving higher capacity by a three-dimensional structure to reduce a bit cost (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2007-266143).
A nonvolatile semiconductor memory to which the BiCS technique is applied (hereinafter referred to as a BiCS memory) does not merely use a three-dimensional structure but also uses a device structure and a process technique that are elaborately designed. This enables bit cost scalability whereby the bit cost decreases in proportion to an increase in the number of stacked layers.
For example, in the case of a NAND-type flash memory to which the BiCS technique is applied (hereinafter referred to as a BiCS-NAND flash memory), the number of cells constituting a NAND array is longitudinally increased due to the increase in the number of stacked layers, thereby obtaining a memory capacity far above the limit of the memory capacity of a two-dimensionally structured NAND-type flash memory.
However, the BiCS memories including the BiCS-NAND flash memory have unique device structures. There are therefore many problems to solve in order to put such memories into practical use.
One of the problems lies in characteristic variations of the memory cells due to variations in shape.
In the BiCS memory, cell units constituting a memory cell array are formed on the side surfaces of a plurality of columnar active layers extending longitudinally to a semiconductor substrate. For example, after a plurality of conductive layers and insulating layers are alternately stacked, a hole extending through these layers is formed by, for example, a reactive ion etching (RIE) method. In this hole, charge storage layers and the columnar active layers are formed. The formed hole and the components formed in this hole are subject to an aspect ratio. This aspect ratio greatly depends on the number of stacked memory cells in the BiCS memory. That is, in the BiCS memory, due to an increase in the number of stacked layers, there may be a difference, between the upper side (bit line side) and the lower side (semiconductor substrate side) of the hole, in the diameter of the columnar active layers and in the thickness of a gate insulating film or the charge storage layer deposited on the side surface of the hole.
As a result, even in the case of the memory cells formed on the side surface of the same one active layer, there is a difference in electric properties including threshold voltages between the memory cells on the upper side of the active layer and the memory cells on lower side of the active layer.